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Frequently Asked Questions in FPC Circuit Design

Author:Luwis zeng Date:5/9/2018 9:37:38 AM
Frequently Asked Questions in FPC Circuit Design

One, pad overlap

1. The overlap of the pads (except the surface mount pads) means that the holes overlap. In the drilling process, the drill bit will be broken due to multiple drill holes in one place, resulting in hole damage.


2. Two holes in the multi-layer board are overlapped, for example, one hole is a spacer disk, and the other hole is a connection disk (flower land), so that the film is depicted as a separation disk, resulting in scrap.

Second, the abuse of the graphic layer

1. Some useless connections were made on some graphic layers. Originally four-layer boards were designed with more than five layers of wires, causing misunderstandings.

2, design time diagram save trouble, using Protel software as an example for each layer of the line with the Board layer to draw, and use the Board layer to mark the line, so when light painting data, because the Board layer is not selected, missed If the connection is disconnected or the circuit is short-circuited due to the selection of the marked line of the board layer, the design layer is kept intact and clear.

3, violation of conventional design, such as the component surface design in the Bottom layer, welding surface design in the Top, causing inconvenience.

Third, the character of random

1. The character cover pad SMD soldering pad brings inconvenience to the on-off test of the printed board and the welding of components.

2, the character design is too small, resulting in screen printing difficulties, too large will make characters overlap each other, difficult to distinguish.

Fourth, single-sided pad aperture settings

1, single-sided pads are generally not drilled, if the drill hole needs to be marked, its aperture should be designed to zero. If a numerical value is designed, when the drilling data is generated, the coordinates of the hole appear at this position and a problem arises.

2, single-sided pads such as drilling should be marked.

Five, draw pads with filler blocks

Drawing pad pads with fillers can be checked by DRC when designing the circuit, but it is not possible to process them. Therefore, the pad cannot directly generate the solder mask data. When the solder resist is applied, the pad area will be covered by the solder mask. Device soldering difficulties.

Sixth, electrical ground is flower pad and connection

Because the power source is designed as a flower pad, the image of the ground and the actual printed board is the opposite. All the connections are isolated lines. Designers should be very clear about this. Here, by the way, care should be taken when painting several sets of power supplies or isolated wires of several grounds, leaving no gaps, shorting the two sets of power supplies, or blocking the area of ​​the connection (making a group of power supplies separated).

Seven, the definition of processing level is not clear

1, single-panel design in the TOP layer, if not stated positive and negative, maybe made of the board installed on the device but not good welding.

2, for example, a four-layer board design using TOP mid1, mid2bottom four layers, but processing is not placed in this order, which requires explanation.

Eight, the design of the filling block is too much or filling blocks with very thin lines

1. There is a phenomenon that the light drawing data is lost, and the light drawing data is incomplete.

2. Because the filling blocks are drawn by lines one by one during the processing of the light drawing data, the amount of light drawing data produced is quite large, which increases the difficulty of data processing.

Nine, surface mount device pad is too short

This is in terms of continuity testing. For too dense surface mount devices, the spacing between the two feet is quite small, the pads are also quite thin, and the test pins must be installed with a vertical (left and right) staggered position, such as a pad The design is too short, although it does not affect the device installation, it will make the test pin out of place.

Tenth, the large area grid spacing is too small

The edges between the lines that make up the large-area grid lines are too small (less than 0.3 mm). During the manufacturing process of the printed circuit board, after the drawing process is completed, many broken films are likely to adhere to the boards, resulting in disconnection.

Eleventh, large area copper foil is too close to the frame

The large area copper foil should be at least 0.2mm away from the outer frame. Due to milling on the copper foil, it can easily cause the copper foil to warp and cause the problem of the solder resist shedding.

Twelve, the shape of the border design is not clear

Some customers have designed the appearance line in Keep layer, Board layer, Top over layer and so on. These appearance lines do not coincide, which makes it difficult for pcb manufacturers to judge which profile line to prevail.

Thirteen, uneven graphic design

When the pattern plating is performed, the plating is uneven and the quality is affected.

14. Apply grid lines when the copper area is too large to avoid foaming at SMT

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